About Me

I work at VMware in VM Monitor team. I completed my Ph.D. in Computer Engineering from Texas A&M University where I worked with Dr. Narasimha Reddy and Dr. Paul V. Gratz. I received my Master and Bachelor degree in Information and Communication Engineering from Shanghai Jiao Tong University, China.

My research interests include computer architecture, emerging memory/storage systems, SW/HW co-design and implementation of computer systems. I worked on several research projects on the emerging Key-Value storage devices (such as Samsung KV-SSDs). My previous work centers on design and implementation of complex high-speed data acquisition and signal processing systems on FPGA platforms. Please see more details on the FPGA projects page.

Working Experience

VMware Inc. (MTS - VM Monitor) May 2020 - Aug 2020, Sep 2021 - now

Las Alomas National Lab (Ultrascale Systems Research Center, Research intern) May 2019 - Aug 2019

Samsung Semiconductor Inc. (Memory Solution Lab, Research intern) May 2018 - Aug 2018

Publications

"KVRAID: High Performance, Write Efficient, Update Friendly Erasure Coding Scheme for KV-SSDs", Mian Qin, Narasimha Reddy, Paul V. Gratz, Rekha Pitchumani, Yang Seok Ki, In The 14th ACM International System and Storage Conference (SYSTOR'21), June 2021.

"FPGA-based Hyrbid Memory Emulation System", F. Wen, M.Qin, P. V. Gratz, N. Reddy, In The 31st International Conference on Field-Programmable Logic and Applications (FPL'21), Aug 2021.

"OpenMem: Hardware/Software Cooperative Management for Mobile Memory System", F. Wen, M.Qin, P. V. Gratz, N. Reddy, In The 58th Design Automation Conference (DAC'21), Dec 2021. (to appear)

HMMU: A Hardware-based Hybrid Memory Management Unit”, F. Wen, M. Qin, P. V. Gratz, N. Reddy, In The 12th Annual Non-Volatile Memories Workshop (NVMW'21) , March 2021.

Hardware Memory Management for Future Mobile Hybrid Memory Systems”, F. Wen, M. Qin, P. V. Gratz, N. Reddy, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ( Volume: 39, Issue: 11, Nov. 2020) .

A Generic FPGA Accelerator for Minimum Storage Regenerating Codes”, M. Qin, J. H. Lee, R. Pitchumani, Y. S. Ki, N. Reddy, P. V. Gratz, In The 25th Asia and South Pacific Design Automation Conference (ASP-DAC'20), Jan 2020.

SPaN: Speculative Paging for future NVM and SSD”, Viacheslav Fedorov, Jinchun Kim, Mian Qin, A. L. Narasimha Reddy and Paul Gratz. In the International Symposium on Memory Systems (MEMSYS’17), October 2017.

Talks

  • KVRAID: High Performance, Write Efficient, Update Friendly Erasure Coding Scheme for KV-SSDs

Systor'21 — Haifa, Israel, Virtual, June 2021 [slides]

Samsung SARC — Posters, Austin, USA, October 2018 [poster]

  • A Generic FPGA Accelerator for Minimum Storage Regenerating Codes

ASP-DAC'20 — Beijing , China, January 2017 [slides]

  • SPaN: Speculative Paging for future NVM and SSD

Memsys'17 — Washington D.C., USA, October 2017 [slides]

Samsung SARC — Posters, Austin, USA, October 2017 [slides, poster]

Patents

US20200192757

FPGA ACCELERATION SYSTEM FOR MSR CODES

CN105680970B

射电天文阵列远程光纤同步系统及其方法(Remote Fiber Array radio astronomy synchronization system and method)

CN105652326A

射电天文阵列的高可扩展性分布式DBF处理系统及方法(High-scalability distributed DBF processing system and method for radio astronomical array)

CN104883156B

基于改进VFDF的实时宽带数字波束指向控制方法(Improved directivity control based on real-time broadband digital beam vfdf)

CN102624357B

一种分数延迟数字滤波器的实现结构(Fractional delay digital filter implementation structure)